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ltc3415 1 3415fa typical application features applications description 7a, polyphase synchronous step-down regulator the ltc ? 3415 is a high ef? ciency, monolithic synchronous buck regulator using a phase lockable constant frequency, current mode architecture. polyphase ? operation allows multiple ltc3415s to run out of phase while using mini- mal input and output capacitance. the operating supply range is from 5.5v down to 2.5v, making it suitable for single lithium-ion battery as well as point of load power supply applications. burst mode operation provides high ef? ciency at low load currents. 100% duty cycle provides low dropout operation that extends operating time in bat- tery-operated systems. the operating frequency is internally set at 1.5mhz, al- lowing the use of small surface mount inductors. for switching-noise sensitive applications, it can be externally synchronized from 0.75mhz to 2.25mhz. the phmode pin allows user control of the phase of the outgoing clock signal. the current sense comparator is factory trimmed for accurate output current sharing. burst mode operation is inhibited during synchronization or when the mode pin is pulled low to reduce noise and rf interference. n point of load power supply n portable instruments n distributed power systems n battery-powered equipment n high ef? ciency: up to 96% n 7a output current at v in = 3v n adjustable frequency: 1.5mhz nominal n polyphase operation (up to 12 phases) n spread spectrum frequency modulation n output tracking and margining n 1% reference accuracy n 2.5v to 5.5v v in range n phase lockable from 0.75mhz to 2.25mhz n selectable burst mode ? operation n low dropout operation: 100% duty cycle n low quiescent current: 450a n current mode operation for excellent line and load transient response n shutdown mode draws only 0.2a supply current n available in 38-pin (5mm 7mm) qfn package figure 1. high ef? ciency step-down converter v out 1.8v 47f x3 22f x3 0.2h 120k 60k ltc3415 pv in v in , 2.5v to 5.5v sv in sgnd pgnd mode fb track run plllpf phmode clkout clkin pgood i th sw sw sw sw sw 3415 ta01 , lt, ltc, ltm, burst mode and polyphase are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131. load current (a) 0.01 efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 power loss (w) 10 1 0.1 0.01 0.001 0.1 1 10 3415 ta01b 2.5v 3.3v 5v efficiency power loss ef? ciency and power loss
ltc3415 2 3415fa absolute maximum ratings pin configuration sv in , pv in voltage ....................................... C0.3v to 6v plllpf, pgood voltages .............................C0.3v to v in clkin, phmode, mode voltages ...............C0.3v to v in clkout voltage .......................................... C0.3v to 2v i th , i thm , v fb , track voltages ....................C0.3v to v in mgn, bsel, run voltages ..........................C0.3v to v in sw voltage (dc) ............................C0.3v to (v in + 0.3v) peak sw sink and source current ............................15a operating ambient temperature range (note 2) ......................................... C40c to 85c junction temperature (note 5) ............................. 125c storage temperature .............................. C65c to 125c (note 1) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v unless otherwise speci? ed. electrical characteristics symbol parameter conditions min typ max units sv in signal input voltage range 2.375 5.5 v v fb regulated feedback voltage (note 3) l 0.590 0.596 0.602 v v fb reference voltage line regulation v in = 2.5v to 5.5v (note 3) 0.15 0.3 %/v v loadreg output voltage load regulation measured in servo loop, v ith = 0.3v measured in servo loop, v ith = 0.9v l l 0.1 C0.05 0.2 C0.2 % % v pgood power good range 7 10 13 % r pgood power good pull-down resistance 1ma load, v in = 3.3v 25 40 order information lead free finish tape and reel part marking package description temperature range ltc3415euhf#pbf ltc3415euhf#trpbf 3415 38-lead (5mm 7mm) qfn package C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ 13 14 15 16 top view uhf package 38-lead (7mm 5mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 39 8 7 6 5 4 3 2 1 nc sgnd plllpf pv in pv in sw sw sw sw mode clkin phmode nc track v fb pv in pv in sw sw sw sw pgood bsel mgn clkout run pv in pv in sv in i thm i th pgnd pgnd pgnd pgnd pgnd pgnd pgnd 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w, jc = 1.1c/w exposed pad (pin 39) is pgnd must be soldered to pcb
ltc3415 3 3415fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3415e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: the ltc3415 is tested in a feedback loop that adjusts v fb to achieve a speci? ed error ampli? er output voltage (i th ). note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient temperature t a and power dissipation as follows: ltc3415: t j = t a + p d (34c/w). note 6: current limit is measured with internal servo loop while forcing v ith = 1v. note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v unless otherwise speci? ed. electrical characteristics symbol parameter conditions min typ max units i q input dc bias current active current sleep shutdown (note 4) v fb = 0.57v, mode = 0v v fb = 0.63v, mode = v in v run = 0v 1350 450 0.2 5 a a a f osc switching frequency 1.3 1.5 1.7 mhz f sync sync capture range 0.75 2.25 mhz r pfet r ds(on) of p-channel fet i sw = 100ma 32 40 m r nfet r ds(on) of n-channel fet i sw = 100ma 25 32 m i limit peak current limit v ith = 1v (note 6) 11 13 15 a v uvlo undervoltage lockout threshold sv in rising sv in falling 2.05 1.85 2.2 2.0 2.35 2.15 v v i lsw sw leakage current v run = 0v, v in = 5.5v 0.1 5 a ss delay internal soft-start delay 140 s g m error ampli? ers transconductance 1.7 2 2.2 mmho run run input threshold run rising run falling 1.4 1.2 1.5 1.3 1.6 1.4 v v pgood delay pgood falling edge delay 35 s % margining output voltage margining percentage mgn hi, bsel low mgn hi, bsel hi mgn hi, bsel = sv in /2 mgn low, bsel low mgn low, bsel hi mgn low, bsel = sv in /2 3 8 13 C3 C8 C13 5 10 15 C5 C10 C15 7 12 17 C7 C12 C17 % % % % % % track tracking threshold (rising) tracking threshold (falling) tracking disable threshold run = v in run = 0v 0.57 0.18 v in C 0.5 v v v v fb slavemode v fb slavemode (ea disable) threshold v in C 0.5 v i th internal switch over threshold for internal compensation v in C 0.5 v ov output overvoltage threshold v fb rising 7 10 13 % uv output undervoltage threshold v fb falling C7 C10 C13 % v hyst ov/uv hysteresis v fb returning to regulation 1 3 %
ltc3415 4 3415fa 40s/div 3415 g08 v in = 3.3v v out = 1.8v forced continuous i load = 0.1a to 5a i out 5a/div i l 5a/ div v out (ac) 100mv/ div temperature (c) C100 r dson (m) 40 35 30 25 20 15 100 3415 g05 C50 0 50 150 power pmos power nmos temperature (c) C100 oscillator frequency (mhz) 100 3415 g11 C50 0 50 150 1.6 1.8 2.0 1.4 1.2 1.0 load current (a) 0 C0.5 load regulation (%) C0.4 C0.2 C0.1 0 0.5 0.2 245 C0.3 0.3 0.4 0.1 1 3 678 3415 g06 fc mode v in = 3.3v v out = 1.8v load current (a) 0.01 efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 power loss (mw) 10 1 0.1 0.01 0.1 1 10 3415 g02 2.5v 3.3v 5v efficiency power loss v out = 1.8v typical performance characteristics r dson vs temperature load regulation (reference figure 13) load step (reference figure 13) oscillator frequency vs temperature ef? ciency and power loss vs load current force continuous mode load current (a) 0.001 efficiency (%) 0.1 100 90 80 70 60 50 40 30 20 10 0 3415 g01 0.01 110 10 1 0.1 0.01 0.001 v out = 1.8v v in = 3.3v % (burst) % (pskip) % (fc) w (burst) w (pskip) w (fc) power loss (mw) ef? ciency and power loss vs load current (3 operating modes) (reference figure 13) supply current vs v in input voltage (v) 2.5 supply current (ma) 4.5 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 3415 g03 3.5 3 5 4 5.5 v o = 1.2v pulse skip v o = 1.2v burst mode r dson vs v in input voltage (v) 2.25 on-resistance (m) 4.25 40 35 30 25 20 15 10 5 0 3415 g04 3.25 5.25 pfet nfet
ltc3415 5 3415fa input voltage (v) 2.5 leakage current (na) 4.5 3415 g12 3 3.5 4 5 5.5 6 200 150 175 100 50 0 125 75 25 main switch synchronous switch 3415 g07 500s/div v out1 = 1.8v/14a 500mv/div v out2 = 3.3v/7a 500mv/div power loss (mw) 10 1 0.1 0.01 0.001 load current (a) 0.01 efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 3415 g09 2.5v 3.3v 5v efficiency power loss v out = 1.8v power loss (mw) 10 1 0.1 0.01 load current (a) 0.01 efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 3415 g10 2.5v 3.3v 5v efficiency power loss v out = 1.8v ef? ciency and power loss burst mode operation output tracking ef? ciency and power loss pulse-skip mode operation switch leakage current vs input voltage typical performance characteristics
ltc3415 6 3415fa functional diagram 29 C + 10 38 12 3 34 2 11 clkin function high low sync spr free-run pll-sync phmode clkout high low float 180 (2-phase) 120 (3-phase) 90 (4-phase) mode function high low float burst-en force-cont. pulse-skip pv in 4,5,27,28,35,36 0.032 sw 6,7,8,9,23,24,25,26 pgnd 13,14,15,16,17,18,19 0.025 anti- shoot- thru tg bg switching logic and blanking circuit rs latch s rq q checks inductor current zero crossing comp for short-circuit protection 20% peak burst clamp sleep C + i rcmp + C nicmp + C + C i comp + C + C + C ovdet + C uvdet + C 50mv burst en 0.2v v in C0.5v 0.54v 0.66v 0.63v 0.6v 0.57v 0.54v 0.66v mode 33 i thminus i thbuf 1.5v clamp i max + slope clamp osc phmode clkout v fb 30 track 37 run 18mhz/12 osc pll spread spectrum v1p8 slope comp intv cc generator clkin plllpf sv in 20 margining mux int. shdn thermal shdn 2v to 2.2v uvlo 0.1ms internal ss mgn 21 bsel sgnd 32 i th ext/int comp 22 pgood ov uv + C ea int. ss ea disable C + v fb comp v in C0.5v 1.5v 0.18v shutdown sv in 3415 fd + C track falling comp C + run comp i th buffer (gm = 2m )
ltc3415 7 3415fa sgnd (pin 2): signal ground. return ground path for all analog and low power circuitry. single connection to pgnd on system board. plllpf (pin 3): phase-locked-loop lowpass filter. the plls lowpass ? lter is tied to this pin. in spread spectrum mode, placing a capacitor here to sgnd controls the slew rate from one frequency to the next. alternatively, ? oating this pin allows normal running frequency at 1.5mhz, tying this pin to sv in forces the part to run at 1.33 times its normal frequency (2mhz), tying it to ground forces the freq uency to run at 0.67 times its normal frequency (1mhz). pv in (pins 4, 5, 27, 28, 35, 36): power v in . input voltage to the on chip power mosfets. must be closely decoupled to pgnd. sw (pins 6, 7, 8, 9, 23, 24, 25, 26): switch node con- nection to the inductor. this pin swings from pv in to pgnd. mode (pin 10): mode select input. tying this pin high enables burst mode operation. tying this pin low enables force continuous operation. tying it to v in /2 enables pulse- skipping operation. clkin (pin 11): external synchronization input to phase detector. this pin is internally terminated to sgnd with a 50k resistor. the phase-locked-loop will force the internal top power pmos turn on to be synchronized with the rising edge of the clkin signal. connect this pin to sv in to enable spread spectrum modulation. during external synchronization, make sure the plllpf pin is not tied to v in or gnd. phmode (pin 12): phase selector input. this pin deter- mines the phase relationship between the internal oscil- lator and clkout. tie it high for 2-phase operation, tie it low for 3-phase operation, and tie it to v in /2 for 4-phase operation. pgnd (pins 13-19): power ground. return path of internal n-channel power mosfets. connect this pin with the (C) terminals of c in and c out . mgn (pin 20): margining pin. tying this pin to a voltage between 0.5v and sv in C 0.5v disables the margining function and allows normal operation. tying it high enables positive margining (5, 10, or 15%). tying it low enables negative margining (C5, C10, or C15%). bsel (pin 21): margining bit select pin. tying bsel low selects 5%, tying it high selects 10%. tying it to v in /2 selects 15%. pgood (pin 22): output power good with open-drain logic. pgood is pulled to ground when the voltage on the v fb pin is not within 10% of its set point. disabled during margining and during slave mode operation (v fb tied to v in ). v fb (pin 29): input to the error ampli? er that compares the feedback voltage to the internal 0.6v reference voltage. this pin is normally connected to a resistive divider from the output voltage. in polyphase operation, tying v fb to sv in disables its own internal error ampli? er and connects the masters i th voltage to its current comparator. track (pin 30): track input pin. this allows the user to control the rise time of the output. putting a voltage below 0.57v on this pin bypasses the reference input into the er- ror ampli? er and servos the v fb pin to the track voltage. above 0.57v, the tracking function stops and the internal reference again controls the error ampli? er. during shut- down, if track is not tied to sv in, then tracks voltage needs to be below 0.18v before the chip shuts down even though run is already low. do not ? oat this pin. i th (pin 32): error ampli? er output and switching regulator compensation point. the current comparators threshold increases with this control voltage. the normal voltage range of this pin is from 0v to 1.5v. its also the positive input to the internal i th differential ampli? er. tying i th to sv in enables the internal compensation. i thm (pin 33): negative input to the internal i th differential ampli? er. tie this pin to sgnd for single phase operation. for polyphase, tie the masters i thm to sgnd while con- necting all of the i thm pins together. sv in (pin 34): signal input voltage. connect this pin to pv in through a 1 and 0.1f lowpass ? lter. run (pin 37): run control input. tying this pin above 1.5v turns on the part. clkout (pin 38): output clock signal for polyphase operation. the phase of clkout is determined by the state of the phmode pin. exposed pad (pin 39): power ground. must be connected to electrical ground on pcb. pin functions
ltc3415 8 3415fa operation main control loop the ltc3415 is a constant frequency, current mode, monolithic step down regulator. in normal operation, the internal top p-channel power mosfet turns on each cycle when the oscillator sets the rs latch, and turns off when the current comparator i comp resets the rs latch. the peak inductor current at which i comp resets the rs latch is controlled by the voltage on the i th pin, which is the output of error ampli? er ea. the fb pin allows ea to receive an output feedback voltage from an external resistive divider. when the load current in- creases, it causes a slight decrease in the feedback volt- age relative to the 0.596v reference, which in turn causes i th voltage to increase until the average inductor current matches the new load current. while the top p-channel power mosfet is off, the bottom n-channel power mosfet is turned on until either the inductor current starts to re- verse, as indicated by the current reversal comparator i rcmp , or the beginning of the next cycle. the main control loop is shut down by pulling the run pin below 1.5v (v track = sv in or v track < 0.18v). tying run higher than 1.5v allows operation to begin. to control the rise time of the output, a voltage ramp can be applied to the track pin. the fb voltage will servo to the track voltage until track goes above 0.57v, which is when pgood is high and the output is in normal regulation. if track is not used (tied high), then an internal 100s soft-start will ramp up the output. burst mode operation the ltc3415 is capable of burst mode operation in which the power mosfets operate intermittently based on load demand, thus saving quiescent current. for applications where maximizing the ef? ciency at very light loads is a high priority, burst mode operation should be applied. to enable burst mode operation, simply tie the mode pin to v in . during this operation, the peak current of the inductor is set to approximately 20% of the maximum peak current value in normal operation even though the voltage at the i th pin indicates a lower value. the voltage at the i th pin drops when the inductors average current is greater than the load requirement. as the i th voltage drops below 0.2v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450a. the load current is now being supplied from the output capacitor. when the output voltage drops, causing i th to rise above 0.25v, the internal sleep line goes low, and the ltc3415 resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. pulse-skipping mode operation in applications where ? xed frequency operation, low output ripple and high ef? ciency at intermediate current is desired, pulse-skipping mode should be used. pulse- skipping operation allows the ltc3415 to skip cycles at low output loads, thus increasing ef? ciency by reducing switching current. tying the mode pin to v in /2 enables pulse-skipping operation. this allows discontinuous conduction mode (dcm) operation down to near the limit de? ned by the chips minimum on-time (about 100ns). below this output current level, the converter will begin to skip cycles in order to maintain output regulation. increasing the output load current slightly, above the minimum required for discontinuous conduction mode, allows constant frequency pwm. forced continuous operation in applications where ? xed frequency operation is more critical than low current ef? ciency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode pin to gnd. in this mode, inductor cur- rent is allowed to reverse during low output loads, the i th voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the ltc3415s output voltage is in regulation.
ltc3415 9 3415fa operation short-circuit protection when the output is shorted to ground, the ltc3415 will drop cycles to allow the inductor time to decay and prevent the current from running away. under this fault condition, the top p-channel power mosfet turns on for a minimum on-time and is held off for as long as it takes for the inductor current to decay to a safe level. output overvoltage if the ltc3415s output voltage exceeds the regulation point by 10%, which is re? ected as a v fb voltage of 0.66v or above, the ltc3415 will attempt to bring back to regu- lation by shutting off the top p-channel power mosfet and turning on the bottom n-channel power mosfet for as long as needed to lower v out . however, if the reverse current ? owing from v out back through the bottom n-channel power mosfet to pgnd is greater than 7a, the ineglim comparator trips and shuts off the bottom n-channel power mosfet to protect it from being de- stroyed. this scenario can happen when the ltc3415 tries to start into a pre-charged load, which could trigger the overvoltage comparator during the time the ltc3415s internal reference is powering up. as a result, the bottom switch turns on until the amount of reverse current trips the ineglim comparator threshold. multiphase operation for output loads that demand more than 7a of current, multiple ltc3415s can be cascaded to run out of phase to provide more output current without increasing input and output voltage ripple. the clkin pin allows the ltc3415 to synchronize to an external clock (between 0.75mhz and 2.25mhz) and the internal phase-locked-loop allows the ltc3415 to lock onto clkins phase as well. the clkout signal can be connected to the clkin pin of the following ltc3415 stage to line up both the frequency and the phase of the entire system. tying the phmode pin to sv in , sgnd, or sv in /2 generates a phase difference (between clkin and clkout) of 180 degrees, 120 degrees, or 90 degrees respectively, which corresponds to 2-phase, 3-phase, or 4-phase operation. a total of 12 phases can be cascaded to run simultaneously out of phase with respect to each s vin s vin 3415 f02a +120 0 phase 1 clkout clkin phmode 180 +120 phase 2 clkout clkin phmode figure 2b. 3-phase operation figure 2a. 2-phase operation figure 2c. 4-phase operation 3415 f02c 0 +90 phase 1 clkout clkin phmode 90 phase 2 clkout clkin phmode 180 +90 +90 phase 3 clkout clkin phmode 270 phase 4 clkout clkin phmode sv in 2 sv in 2 sv in 2 sv in 2 3415 f02b 0 +120 phase 1 clkout clkin phmode 120 phase 2 clkout clkin phmode 240 +120 phase 3 clkout clkin phmode
ltc3415 10 3415fa operation other by programming the phmode pin of each ltc3415 to different levels. for example, a slave stage that is 180 degrees out of phase from the master can generate a clkout signal that is 300 degrees (phmode = 0) away from the master for the next stage, which then can gener- ate a clkout signal thats 420, or 60 degrees (phmode = sv in /2) away from the master for its following stage. figure 2d. 6-phase operation 3415 f02d 0 +120 phase 1 clkout clkin phmode 120 phase 3 clkout clkin phmode 240 +180 +120 phase 5 clkout clkin phmode s vin (420) 60 phase 2 clkout clkin phmode +120 180 phase 4 clkout clkin phmode +120 300 phase 6 clkout clkin phmode sv in 2 figure 2e. 12-phase operation 0 +90 phase 1 3415 f02e clkout clkin phmode 90 phase 4 clkout clkin phmode 240 +90 phase 9 clkout clkin phmode 330 phase 12 clkout clkin phmode 180 +90 +90 phase 7 clkout clkin phmode 270 phase 10 clkout clkin phmode +120 +90 (390) 30 phase 2 clkout clkin phmode 120 +90 phase 5 clkout clkin phmode 210 phase 8 clkout clkin phmode 300 +120 +90 phase 11 clkout clkin phmode (420) 60 phase 3 clkout clkin phmode +90 +90 150 phase 6 clkout clkin phmode sv in 2 sv in 2 sv in 2 sv in 2 sv in 2 sv in 2 sv in 2 sv in 2 sv in 2 sv in 2 refer to figure 2 for con? gurations of 2-phase, 3-phase, 4-phase, 6-phase and 12-phase operation. a multiphase power supply signi? cantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is divided by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number
ltc3415 11 3415fa figure 3. single and 2-phase current waveforms 3415 f03 sw1 v i cin i cout single phase sw1 v sw2 v i cin i l2 i l1 i cout dual phase ripple operation of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used. figure 3 graphically illustrates the principle. the worst-case rms ripple current for a single stage design peaks at an input voltage of twice the output voltage. the worst case rms ripple current for a two stage design re- sults in peak outputs of 1/4 and 3/4 of input voltage. when the rms current is calculated, higher effective duty factor results and the peak current levels are divided as long as the current in each stage is balanced. refer to application note 19 for a detailed description of how to calculate rms current for the single stage switching regulator. figures 4 and 5 illustrate how the input and output currents are reduced by using an additional phase. for a 2-phase converter, the input current peaks drop in half and the frequency is doubled. the input capacitor requirement is thus reduced theoretically by a factor of four! just imagine the possibility of capacitor savings with even higher number of phases! output current sharing when multiple ltc3415s are cascaded to drive a com- mon load, accurate output current sharing is essential to achieve optimal performance and ef? ciency. otherwise, if one stage is delivering more current than another, then the temperature between the two stages will be different, and that could translate into higher switch r ds(on) , lower ef? ciency, and higher rms ripple. each ltc3415 is trimmed such that when the i th pins of multiple ltc3415s are tied together, the amount of output current delivered from each ltc3415 is nearly the same. different ground potentials among ltc3415 stages, caused by physical distances and ground noises, could cause an offset to the absolute i th value seen by each stage. to ensure that the ground level doesnt affect the i th value, the ltc3415 uses a differential driver that takes as input not just the i th pin, but also the i thm pin. the i thm pins of all the ltc3415 stages should be tied together and then connected to the sgnd at only one point. figure 4. normalized output ripple current vs duty factor [i rms ? 0.3 (di c(pp) )] figure 5. normalized rms input ripple current vs duty factor for 1 and 2 output stages duty factor (v out /v in ) 0.1 di c(p-p) v o /l 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.3 0.5 0.6 3415 f04 0.2 0.4 0.7 0.8 0.9 1 phase 2 phase 0 0.1 0.2 0.3 0.4 3415 f05 0.5 0.6 duty factor (v out /v in ) 0.1 rms input ripple current dc load current 0.3 0.5 0.6 0.2 0.4 0.7 0.8 0.9 1 phase 2 phase
ltc3415 12 3415fa operation phase-locked-loop operation in order to synchronize to an external signal, the ltc3415 has an internal phase-locked-loop comprised of an in- ternal voltage controlled oscillator and phase detector. this allows the top p-channel power mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is +50% around the center frequency. leaving the plllpf pin ? oating corresponds to a free-running frequency of approximately 1.5mhz. tying plllpf directly to sv in corresponds to 1.33x of center frequency (2mhz) while tying plllpf to ground corresponds to 0.67x of center frequency (1mhz). the phase detector used is an edge sensitive digital type which provides zero degree phase shift between the external and internal oscillators. the output of the phase detector is a complementary pair of current sources charging or discharging the external ? lter network on the plllpf pin. see figure 6. if the external frequency, clkin, is greater than the os- cillator frequency f osc , current is sourced continuously, pulling up the plllpf pin. when the external frequency is less than f osc , current is sunk continuously, pulling down the plllpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. thus the voltage on the plllpf pin is adjusted until the phase and frequency of the external and internal oscillators are identical. the clkin pin must be driven from a low impedance source such as a logic gate located close to the pin. the loop ? lter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the ? lter components determine how fast the loop acquires lock. typically r lp = 10k and c lp is 100pf to 1000pf. the clkout pin provides a signal to synchronize follow- ing stages of ltc3415s. its amplitude is 0v to 2v and its phase with respect to the internal oscillator (or clkin) is controlled by the phmode pin. internal/external i th compensation during single phase operation, the user can simplify the loop compensation by tying the i th pin to sv in to enable internal compensation. this connects an internal 50k resistor in series with a 50pf cap to the output of the error ampli? er (internal i th compensation point). this is a trade-off for simplicity instead of opti-loop ? optimiza- tion, where i th components are external and are selected to optimize the loop transient response with minimum output capacitance. see checking transient response in the applications information section. opti-loop is a registered trademark of linear technology corporation. figure 6. phase-locked-loop block diagram 3415 f06 r lp 10k c lp plllpf clkin osc 2v digital phase frequency detector phase detector external osc 50k
ltc3415 13 3415fa frequency (mhz) 1.0 amplitude (dbm) C50 C30 C10 1.8 3415 f08 C70 C90 C60 C40 C20 C80 C100 1.2 1.1 1.4 1.3 1.6 1.7 1.9 1.5 2.0 v in = 5v v out = 1.8v rbw = 100hz C37.3dbm frequency (mhz) 1.0 amplitude (dbm) C50 C30 C10 1.8 3415 f07 C70 C90 C60 C40 C20 C80 C100 1.2 1.1 1.4 1.3 1.6 1.7 1.9 1.5 2.0 v in = 5v v out = 1.8v rbw = 100hz C14.1dbm in multiphase operation where all the i th pins of each ltc3415 are tied together to achieve accurate load sharing, internal compensation is not allowed. external compensa- tion components need to be properly selected for optimal transient response and stable operation. master/slave operation in multiphase single-output operation, the user has the option to run in multi-master mode where all the v fb , i th , and output pins of the stages are tied to each other. all the error ampli? ers are effectively operating in parallel and the total g m of the system is increased by the number of stages. the i th value, which dictates how much current is delivered to the load from each stage, is averaged and smoothed out by the external i th compensation compo- nents. however, in certain applications, the resulting higher g m from multiple ltc3415s can make the system loop harder to compensate. in this case, the user can choose an alternative mode of operation. the second mode of operation is single-master operation where only the error ampli? er of the master stage is used while the error ampli? ers of the other stages (slaves) are disabled. the slaves error ampli? er is disabled by tying its v fb pin to sv in , which also disables the internal over- voltage comparator and power-good indicator. the masters error ampli? er senses the output through its v fb pin and drives the i th pins of all the stages. to account for ground voltage differences among the stages, the user should tie all i thm pins together and then tie it to the masters signal ground. as a result, not only is it easier to do loop compensation, this single-master operation should also provide for more accurate current sharing among stages because it prevents the error ampli? ers output (i th ) of each stage from interfering with that of another stage. spread spectrum operation switching regulators can be particularly troublesome where electromagnetic interference (emi) is concerned. switching regulators operate on a cycle-by-cycle basis to transfer power to an output. in most cases, the frequency of operation is ? xed or is a constant based on the output load. this method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency (harmonics). to reduce this noise, the ltc3415 can run in spread spectrum operation by tying the clkin pin to sv in . in spread spectrum operation, the ltc3415s internal oscil- lator is designed to produce a clock pulse whose period is random on a cycle-by-cycle basis but ? xed between 70% and 130% of the nominal frequency. this has the bene? t of spreading the switching noise over a range of frequencies, thus signi? cantly reducing the peak noise. figures 7 and 8 show how the spread spectrum feature of the ltc3415 signi? cantly reduces the peak harmonic figure 8. ltc3415s output noise spectrum analysis in spread spectrum operation figure 7. ltc3415s output noise spectrum analysis in free-running constant frequency operation operation
ltc3415 14 3415fa operation noise vs free-running constant frequency operation. spread spectrum operation is disabled if clkin is tied to ground or if its driven by an external frequency synchronization signal. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle will increase toward the maximum on-time. further reduction of the supply voltage forces the p-channel power mosfet to remain on for more than one cycle until it reaches 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the p-channel power mosfet and the inductor. slope compensation and inductor peak current slope compensation provides stability by preventing sub- harmonic oscillations. it works by internally adding a ramp to the inductor current signal at duty cycles in excess of 30%. this causes the internal current comparator to trip earlier. the i th clamp is also reached earlier than condi- tions in which the duty cycle is below 30%. as a result, the maximum inductor peak current is lower for higher duty cycle operations. to compensate for this loss in maximum inductor peak current during high duty cycles, the ltc3415 uses a pat- ented scheme that raises the i th clamp level (proportional to the amount of slope compensation) when the duty cycle is greater than 30%. minimum on-time considerations minimum on-time, t on(min) , is the smallest amount of time that the ltc3415 is capable of turning the top p-channel power mosfet on and off again. it is determined by the internal timing delays. the minimum on-time for the ltc3415 is about 100ns. low duty cycle and high frequency applications may approach this minimum on- time limit and care should be taken to ensure that: t on(min) < v out (f ? v in ) if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc3415 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. if an application can operate close to the minimum on-time limit, an inductor must be chosen that has low enough inductance to provide suf? cient ripple amplitude to meet the minimum on-time requirement. as a general rule, keep the inductor ripple current equal or greater than 30% of the i out(max) at v in(max) . output margining for a convenient system stress test on the ltc3415s out- put, the user can program the ltc3415s output to 5%, 10% or 15% of its normal operational voltage. the mgn pin, when connected to a voltage between 0.5v and sv in C 0.sv allows normal operation. when the mgn pin is low, it forces negative margining, in which the output voltage is below the regulation point. when mgn is high, the output voltage is forced to above the regulation point. the amount of output voltage margining is determined by the bsel pin. when bsel is low, its 5%. when bsel is high, its 10%. when bsel is v in /2, its 15%. when margining is active, the internal output overvoltage and undervoltage comparators are disabled and pgood remains high. output power-good when the ltc3415s output voltage is within a 10% window of the regulation point, which is re? ected back as a v fb voltage in the range of 0.54v to 0.66v, the output voltage is good and the pgood pin is pulled high with the external resistor.
ltc3415 15 3415fa figure 9. setting the output voltage otherwise, an internal open-drain pull down device (20) will pull the pgood pin low. in certain computer systems today, the pgood pin is used as a resetting signal while the output voltage is dynamically changed from one level to another. to prevent unwanted power resetting during output voltage changes, the ltc3415s pgood falling and rising edges include a blanking delay equivalent to approximately 10s per every volt of v in . output voltage programming the output voltage is set by an external resistive divider according to the following equation: v out = 0.596v ? 1 + r2 r 1 the resistive divider allows pin v fb to sense a fraction of the output voltage as shown in figure 9. output tracking and sequencing some microprocessor, asic and dsp chips need two power supplies with different voltage levels. these sys- tems often require voltage sequencing between the core power supply and the i/o power supply. without proper sequencing, latch-up failure or excessive current draw may occur that could result in damage to the processors i/o ports or the i/o ports of supporting system devices such as memory, fpgas or data converters. to ensure that the i/o loads are not driven until the core voltage is properly biased, tracking of the core supply voltage and the i/o supply voltage is necessary. voltage tracking is enabled by applying a voltage to the track pin. when the voltage on the track pin is below 0.57v, the feedback voltage will regulate to this tracking voltage. when the tracking voltage exceeds 0.57v, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. voltage tracking the ltc3415 allows the user to program how its output voltage ramps during start-up by means of the track pin. through this pin, the output voltage can be set up to either coincidentally or ratiometrically track another output voltage as shown in figure 10. figure 10. two different modes of output voltage sequencing (10a) coincident tracking (10b) ratiometric sequencing operation ltc3415 sgnd r1 3415 f09 r2 v fb v out c ff time v out2 v out1 output voltage time 3415 f10 v out2 v out1 output voltage
ltc3415 16 3415fa if the voltage on the track pin is less than 0.57v, voltage tracking is enabled. during voltage tracking, the output voltage is regulated by the tracking voltage through a resis- tive divider network. the output voltage during tracking can be calculated with the following equation: v out = v track 1 + r2 r 1 ,v track < 0.57v voltage tracking can be accomplished by sensing a frac- tion of the output voltage from another regulator. this is typically done by using a resistive divider to attenuate the output voltage that is being tracked. setting this resistive divider equal to the feedback resistive divider will force the regulator outputs to be equal to each other during track- ing. if tracking is not desired, connect the track pin to sv in. do not leave the track pin ? oating. to implement the coincident tracking shown in figure 10a, connect an extra resistive divider to the output of v out2 and connect operation its midpoint to the track pin of the ltc3415 as shown in figure 11. the ratio of this divider should be selected the same as that of v out1 s resistive divider. to implement the ratiometric sequencing in figure 10b, no extra resis- tive divider is necessary. simply connect the track pin to v fb of the master. an alternative method of tracking is shown in figure 12. for the circuit of figure 12, the following equations can be used to determine the resistor values: v out1 = 0.596v 1 + r2 r 1 v out2 = 0.596v 1 + r4 + r5 r 3 r4 = r3 v out2 v out 1 ?1 figure 12. dual voltage system with tracking figure 11. setup for tracking and ratiometric sequencing (11a) coincident tracking setup (11b) ratiometric setup r4 r2 r3 r1 to v fb2(master) pin to track pin v out2 r2 r1 3415 f11 to v fb2(master) pin to track pin v out2 ltc3415 sgnd r1 3415 f12 r2 v fb track v out1 ltc3415 sgnd r3 r4 r5 v fb v out2
ltc3415 17 3415fa during ramp down of the output, if the track pin is not tied to v in , then the ltc3415 will maintain normal opera- tion even though the run pin is programmed low. only when the track pin is below 0.18v will the run signal be gated through internally and shut down the part. this way, coincident tracking and ratiometric sequencing of the two outputs are accomplished during both start-up and shutdown. an output current load, however, needs to be present during this time in order to discharge the output because when track is below 0.57v, forced continuous operation is not allowed and inductor current, therefore, is prevented from going negative. for applications that do not require tracking or sequenc- ing, simply tie the track pin to sv in to let run control the turn on/off of the ltc3415. connecting track to sv in also enables the ~100s of internal soft-start during start-up. operation
ltc3415 18 3415fa c in and c out selection the input capacitance, c in , is needed to ? lter the trapezoidal wave current at the source of the top mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current should be used. the maximum rms current is given by: i rms ? i out(max) v out v in v in v out ?1 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, suf? cient bulk input capacitance is needed to minimize transient effects during output load changes. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, v out , is determined by: v out i l esr + 1 8fc ou t the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capaci- tors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have signi? cantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics and small footprints. their relatively low value of bulk capacitance may require multiples in parallel. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. applications information
ltc3415 19 3415fa inductor selection given the desired input and output voltages, the induc- tor value and operating frequency determine the ripple current: i l = v out f l 1? v out v i n lower ripple current reduces cores losses in the inductor, esr losses in the output capacitors, and output voltage ripple. highest ef? ciency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, ef? ciency, and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a speci? ed maximum, the induc- tance should be chosen according to: l = v out f i l(max ) 1? v out v in(max ) once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a ? xed inductor value, but is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/cur- rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated ? eld/emi requirements. new designs for surface mount inductors are available from coiltronics, coilcraft, toko, and sumida. checking transient response the opti-loop compensation allows the transient re- sponse to be optimized for a wide range of loads and output capacitors. the availability of the i th pin not only allows optimization of the control loop behavior but also provides a dc-coupled and ac ? ltered closed loop response test point. the dc step, rise time and settling at this test point truly re? ects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 12 circuit will provide an adequate starting point for most applica- tions. the series r-c ? lter sets the dominant pole-zero loop compensation. the values can be modi? ed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. applications information
ltc3415 20 3415fa switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im- mediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. the gain of the loop increases with the r and the bandwidth of the loop increases with decreasing c. if r is increased by the same factor that c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, a feed forward capacitor c f can be added to improve the high frequency response, as shown in figure 9. capacitor c f provides phase lead by creating a high frequency zero with r2 which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to linear technology application note 76. although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage v in drops toward v out , the load step capability does decrease due to the decreasing voltage across the inductor. applications that require large load step capabil- ity near dropout should use a different topology such as sepic, zeta, or single inductor, positive buck/boost. in some applications, a more severe transient can be caused by switching in loads with large (>10f) input capacitors. the discharged input capacitors are effec- tively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap ? controller is designed speci? cally for this purpose and usually incorporates current limiting, short-circuit protec- tion, and soft-starting. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: % ef? ciency = 100% C (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3415 circuits: 1) ltc3415 v in current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1) the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (<1%) loss that increases with v in , even at no-load. 2) the switching current is the sum of the mosfet driver and control currents. the mosfet driver current re- sults from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continuous mode, i gatechg = f (qt + qb), where qt and qb are the gate charges of the internal top and bottom mosfet switches and f is the operat- ing frequency. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages and higher switching frequencies. hot swap is a trademark of linear technology corporation. applications information
ltc3415 21 3415fa 3) i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current ? ows through inductor l but is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on) top)(dc) + (r ds(on) bot)(1-dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 4) other hidden losses such as copper trace and in- ternal battery resistances can account for additional ef? ciency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by ensuring that c in has adequate charge storage and very low esr at the switching frequency. other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. thermal considerations in the majority of applications, the ltc3415 does not dissipate much heat due to its high ef? ciency. however, in applications where the ltc3415 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3415 from exceeding the maximum junc- tion temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as an example, consider the case when the ltc3415 is in dropout at an input voltage of 3.3v with a load current of 5a. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the p- channel switch is 0.03. therefore, power dissipated by the part is: p d = i 2 ? r ds(on) = 750mw the qfn 5mm 7mm package junction-to-ambient thermal resistance, ja , is around 34c/w. therefore, the junction temperature of the regulator operating in a 50c ambient temperature is approximately: t j = 0.75 ? 34 + 50 = 75.5c remembering that the above junction temperature is obtained from an r ds(on) at 25c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. however, we can safely as- sume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125c. solder the ltc3415s bottom exposed pad to ground for optimal thermal performance. applications information
ltc3415 22 3415fa board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3415. check the following in your layout: 1) do the capacitors c in connect to the power pv in and power pgnd as closely as possible? these capacitors provide the ac current to the internal power mosfets and their drivers. 2) are the c out and l1 closely connected? the (C) plate of c out returns current to pgnd and the (C) plate of c in . 3) the resistive divider, r1 and r2, must be connected between the (+) plate of c out and a ground line termi- nated near sgnd. the feedback signal v fb should be routed away from noisy components and traces, such as the sw line, and its trace should be minimized. 4) keep sensitive components away from the sw pin. the input capacitor c in , the compensation capacitor c c and c ith and all the resistors r1, r2, r c should be routed away from the sw trace and the inductor l1. 5) a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the sgnd pin at one point which is then connected to the pgnd pin. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. these copper areas should be connected to one of the input supplies: pv in , pgnd, sv in , or sgnd. design example as a design example, consider using the ltc3415 in an application with the following speci? cations: v in = 3.3v, v out = 1.8v, i out(max) = 7a, i out(min) = 500ma, f = 1.5mhz because ef? ciency is important at both high and low load current, burst mode operation or pulse-skipping operation will be utilized. first calculate the inductor value for about 40% ripple current at maximum v in : l = 1.8v 1.5mhz ? 2.8 a 1? 1.8v 3.3 v = 0.2 h c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design, two 100f ceramic capacitors will be used. c in should be sized for a maximum current rating of: i rms = 7a 2.5v 4.2 v 4.2v 2.5 v ? 1 = 3.43a decoupling the pv in pins with three 47f ceramic capaci- tors is adequate for most applications. applications information
ltc3415 23 3415fa 13 14 15 16 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 23 22 21 20 9 10 11 12 mode clkin phmode sv in v in v out 1.8v/7a bsel 10k mgn 10k 15k 1 30.5k 0.1f 100f, 6.3v 2x pgnd (39) ltc3415euhf clkout run pv in pv in sv in i thm i th pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw sw pv in pv in plllpf sgnd sgnd 0.2h nc sw mode clkin phmode sw sw sw pv in pv in v fb track sv in nc sw pgood bsel mgn 10pf 100pf 47f 6.3v 3x 3415 ta02 typical applications figure 13. 3.3v to 1.8v/7a application
ltc3415 24 3415fa dual ltc3415 dual output sequencing application 13 14 15 16 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 23 22 21 20 9 10 11 12 clkin sgnd sv in sv in v in v out (2.5v) v out (1.8v) v out (1.8v) bsel 100k mgn 10k 9.53k 10k 1000pf 100pf 1 30.5k 0.1f 0 .01f pgnd (39) ltc3415euhf clkout run shdnb pv in pv in sv in i thm i th pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw sw pv in pv in plllpf sgnd 0.2h nc sw mode clkin phmode sw sw sw pv in pv in v fb track sv in nc sw pgood bsel mgn 10pf 100pf 22f 3x 13 14 15 16 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 23 22 21 20 9 10 11 12 clkin2 phmode sgnd sv in v in bsel sv in 100k mgn 100k 10k 15k 10k 1000pf 100pf 1 30.5k 0.1f 47f 3x pgnd (39) ltc3415euhf clkout run pv in pv in sv in i thm i th pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw sw pv in pv in plllpf sgnd sgnd shdnb 0.2h nc sw mode clkin phmode sw sw sw pv in pv in v fb track nc sw pgood bsel mgn 10pf 100pf 22f 3x 3415 ta05 47f 3x output sequencing shdnb v out1 = 2.5v v out2 = 1.8v 100k typical applications
ltc3415 25 3415fa 13 14 15 16 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 23 22 21 20 9 10 11 12 v in v in bsel mgn 10k 1 0.1f 100f 6.3v 2x pgnd (39) ltc3415euhf clkout2 run pv in pv in sv in i thm i th pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw sw pv in pv in plllpf sgnd sgnd 0.2h 0.2h nc sw mode clkin phmode sw sw sw pv in pv in v fb track nc sw pgood bsel mgn 10pf 100pf 22f 6x 3415 ta03 13 14 15 16 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 23 22 21 20 9 10 11 12 sv in sv in v out 1.8v/14a bsel 10k mgn 15k 10k 1000pf 100pf 1 30.5k 0.1f pgnd (39) ltc3415euhf clkout run run pv in pv in sv in i thm i th pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw sw pv in pv in plllpf sgnd sgnd nc sw mode clkin phmode sw sw sw pv in pv in v fb track v track nc sw pgood bsel mgn sv in dual ltc3415 single output 14a application typical applications
ltc3415 26 3415fa 13 14 15 16 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 23 22 21 20 9 10 11 12 clkin sv in sv in v in bsel 10k mgn 10k 9.53k 10k 1000pf 100pf 1 3.7k 26.7k 0.1f pgnd (39) ltc3415euhf clkout run run pv in pv in sv in i thm i th pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw sw pv in pv in plllpf sgnd 0.2h nc sw mode clkin phmode sw sw sw pv in pv in v fb track sv in nc sw pgood bsel mgn 10pf 100pf 22f 6.3v 3x 13 14 15 16 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 23 22 21 20 9 10 11 12 clkin2 phmode sv in v in v out 1.8v/7a bsel 10k mgn 10k 15k 10k 1000pf 100pf 1 30.5k 0.1f 47f, 6.3v 3x v out 2.5v/7a pgnd (39) ltc3415euhf clkout run run pv in pv in sv in i thm i th pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw sw pv in pv in plllpf sgnd sgnd 0.2h nc sw mode clkin phmode sw sw sw pv in pv in v fb track nc sw pgood bsel mgn 10pf 100pf 22f 6.3v 3x 3415 ta04 47f, 6.3v 3x dual ltc3415 dual output tracking application typical applications
ltc3415 27 3415fa 5.00 p 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom viewexposed pad 5.50 ref 5.15 0.10 7.00 p 0.10 0.75 p 0.05 r = 0.125 typ r = 0.10 typ 0.25 p 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 C 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 p 0.10 0.70 p 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 p 0.05 5.50 p 0.05 5.15 0.05 6.10 p 0.05 7.50 p 0.05 0.25 p 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description
ltc3415 28 3415fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0508 rev a ? printed in usa part number description comments ltc3404 600ma i out , 1.4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.7v to 6v, v out(min) = 0.8v, i q = 10a, i sd = <1a, ms8 package ltc3405/ ltc3405a 300ma i out , 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 20a, i sd = <1a, thinsot package ltc3406/ ltc3406b 600ma i out , 1.5mhz, synchronous step-down dc/dc converter 96% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, i sd = <1a, thinsot package ltc3407 dual 600ma i out , 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd = <1a, ms10e package ltc3411 1.25a i out , 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd = <1a, ms10 package ltc3412 2.5a i out , 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd = <1a, tssop16e package ltc3413 3a i out sink/source, 2mhz, monolithic synchronous regulator for ddr/qdr memory termination 90% ef? ciency, v in : 2.25v to 5.5v, v out(min) = v ref/2 , i q = 280a, i sd = <1a, tssop16e package ltc3414 4a i out , 4mhz, synchronous monolithic step-down regulator 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd = <1a, tssop20e package ltc3416 4a i out , 4mhz, synchronous monolithic step-down regulator with tracking 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd = <1a, tssop20e package ltc3418 8a i out , 4mhz, synchronous monolithic step-down regulator v in : 2.25v to 5.5v, v out(min) = 0.8v, 5mm 7mm gfn package ltc3425 5a i out , 8mhz, 4-phase synchronous step-up dc/dc converter 5% ef? ciency, v in : 0.5v to 4.5v, v out(max) = 5.25v, i q = 12a, i sd = <1a, qfn package ltc3428 4a i out , 2mhz, dual phase step-up dc/dc converter 92% ef? ciency, v in : 1.6v to 4.5v, v out(max) = 5.25v, i q = 1.3ma, i sd = <1a, dfn package lt3430 60v, 2.75a i out , 200khz, high ef? ciency step-down dc/dc converter 90% ef? ciency, v in : 5.5v to 60v, v out(min) = 1.20v, i q = 2.5ma, i sd = 25a, tssop16e package ltc3440 600ma i out , 2mhz, synchronous buck-boost dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 2.5v, i q = 25a, i sd = <1a, ms-10 package ltm4600 10a, dc/dc module complete synchronous power supply in lga; 4.5v v in 28v; 15mm 15mm 2.8mm lga package related parts

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